VLSI design for analog neural computation

information into the cell body, and transmit the output electrical signals through the axon. The paper describes a VLSI design methodology for the implementation of analog artificial neural networks. Analog VLSI circuit techniques offers area-efficient implementation of the functions required in a neural network such as multiplication, summation and Sigmoid transfer function. However, the analog circuits are sensitive to the problems of process variation, device matching, and cascadeability. For this reason, special attention must be given to the limitations of the MOS transistor and to the design techniques. As result, in analog neural hardware the high accuracy and linearity found in digital implementations is traded off for the simplicity, speed, silicon area and interconnectivity found in analog circuits. The smaller linearity of the synapses based on four quadrant analog multipliers can be compensated by increasing the design effort at the circuit and layout level. The multipliers utilised in the actual implementation consists of four quadrant CMOS analog multipliers based on voltage resistors (VCR). For the VLSI architecture of the neural network system, a description of each analog circuit block is provided. The circuits presented were designed in a 2 μm CMOS process with two layers of metalization and two layers of polysilicon. Artificial neural networks are inspired from biology and represent massively parallel computer systems that have the ability to generalise, adapt and learn from experience, once they have been properly trained using a training algorithm. The basic building blocks for artificial neural networks are neurons and synapses. Each synapse multiplies an input by a stored weight, and each neuron takes the outputs of several synapses, sums them and then passes them through a transfer or activation function [12]. Research on the applications of neural networks is performed using software, hardware and optical implementations of these networks [11]. The hardware implementations ranging from digital, mixed analogdigital/pulse stream to analog offer the performances required to fully capitalise on the potential of the neural networks implemented. However, the main challenge facing hardware implementation is the number of connections required. An analog VLSI design methodology is discussed in this paper. The analog neural networks implementation offers the advantages of high speed, low power consumption, small silicon area and simple circuitry. 2. ARCHITECTURAL DESCRIPTION The architecture is well suited for descent based learning algorithms such as Back Propagation and Weight Perturbation. Each synapse is implemented using a simple multiplier based on voltage controlled resistors (VCR). The differential output current from the analog multiplier is passed to a current conveyor that has the role of maintaining the virtual short between V1 and V2. The differential output current from the current conveyor of each synapse is summed into a common bus and transformed into a differential voltage output using an active load circuit.